A study of carrier-trap generation by Fowler-Nordheim tunneling stress on polycrystalline-silicon/SiO₂/silicon structures

Deep level transient spectroscopy was used to study carrier traps induced in n⁺-polycrystalline-silicon/90 Å-thick SiO₂/p-type silicon material-system capacitors. The capacitors were fabricated using a 0.50 μm complementary metal-oxide-silicon (CMOS) process flow. The capacitor structures were subjected to constant-voltage Fowler-Nordheim (FN) stressing at temperatures between 50 and 300 K. It was observed that stressing at temperatures above 150 K induces a 0.20 eV-wide band of closely-spaced SiO₂/Si interface hole-traps centered at 0.55 eV above the edge of the valence band in silicon. For the same stress level, the concentration of traps in the band decreases with decreasing temperature, and the band is undetectable at stress temperatures below 150 K. FN stress at temperatures of 150 K and below is observed to induce defect states in the silicon substrate 600-1000 Å below the interface. The silicon defects observed in this study give rise to electron traps at 0.30, 0.35, and 0.37 eV below the bottom of the conduction band. The former two traps are suggested to arise from the configurationally bistable boron vacancy pair. The latter trap, which is unstable above ∼150 K, is tentatively ascribed to the isolated vacancy.