A study of reduced-terminal models for system-level SSO noise analysis

Myunghyun Ha; Joong Ho Kim; Dan Oh; Madhavan Swaminathan

doi:10.1109/EPEPS.2010.5642541

A study of reduced-terminal models for system-level SSO noise analysis

Myunghyun Ha, Joong Ho Kim, Dan Oh, Madhavan Swaminathan

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.

Original language	English (US)
Title of host publication	2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010
Publisher	IEEE Computer Society
Pages	49-52
Number of pages	4
ISBN (Print)	9781424468652
DOIs	https://doi.org/10.1109/EPEPS.2010.5642541
State	Published - 2010

Publication series

Name	2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/EPEPS.2010.5642541

Cite this

Ha, M., Kim, J. H., Oh, D., & Swaminathan, M. (2010). A study of reduced-terminal models for system-level SSO noise analysis. In 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010 (pp. 49-52). Article 5642541 (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010). IEEE Computer Society. https://doi.org/10.1109/EPEPS.2010.5642541

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abstract = "SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.",

author = "Myunghyun Ha and Kim, {Joong Ho} and Dan Oh and Madhavan Swaminathan",

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doi = "10.1109/EPEPS.2010.5642541",

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Ha, M, Kim, JH, Oh, D & Swaminathan, M 2010, A study of reduced-terminal models for system-level SSO noise analysis. in 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010., 5642541, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, IEEE Computer Society, pp. 49-52. https://doi.org/10.1109/EPEPS.2010.5642541

A study of reduced-terminal models for system-level SSO noise analysis. / Ha, Myunghyun; Kim, Joong Ho; Oh, Dan et al.
2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. IEEE Computer Society, 2010. p. 49-52 5642541 (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.

AB - SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.

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Ha M, Kim JH, Oh D, Swaminathan M. A study of reduced-terminal models for system-level SSO noise analysis. In 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. IEEE Computer Society. 2010. p. 49-52. 5642541. (2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010). doi: 10.1109/EPEPS.2010.5642541

A study of reduced-terminal models for system-level SSO noise analysis

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