A study on performance and power efficiency of dense non-volatile caches in multi-core systems

Amin Jadidi; Mohammad Arjomand; Mahmut Kandemir; Chita Das

doi:10.1145/3078505.3078547

A study on performance and power efficiency of dense non-volatile caches in multi-core systems

Amin Jadidi
, Mohammad Arjomand
, Mahmut Kandemir
, Chita Das

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM). Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other half are write-friendly -This asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC) mode. Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache (L3) access energy for various workloads.

Original language	English (US)
Title of host publication	SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems
Publisher	Association for Computing Machinery, Inc
Pages	27-28
Number of pages	2
ISBN (Electronic)	9781450350327
DOIs	https://doi.org/10.1145/3078505.3078547
State	Published - Jun 5 2017
Event	2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017 - Urbana-Champaign, United States Duration: Jun 5 2017 → Jun 9 2017

Publication series

Name	SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

Other

Other	2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017
Country/Territory	United States
City	Urbana-Champaign
Period	6/5/17 → 6/9/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 10 Reduced Inequalities

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Computer Networks and Communications
Computational Theory and Mathematics

Access to Document

10.1145/3078505.3078547

Cite this

Jadidi, A., Arjomand, M., Kandemir, M., & Das, C. (2017). A study on performance and power efficiency of dense non-volatile caches in multi-core systems. In SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems (pp. 27-28). (SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems). Association for Computing Machinery, Inc. https://doi.org/10.1145/3078505.3078547

Jadidi, Amin ; Arjomand, Mohammad ; Kandemir, Mahmut et al. / A study on performance and power efficiency of dense non-volatile caches in multi-core systems. SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. Association for Computing Machinery, Inc, 2017. pp. 27-28 (SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems).

@inproceedings{b7bf03c4aee2417e96914754882b5b54,

title = "A study on performance and power efficiency of dense non-volatile caches in multi-core systems",

abstract = "This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM). Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other half are write-friendly -This asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC) mode. Our experiments show that our design gives an average improvement of 12\% in system performance and 26\% in last-level cache (L3) access energy for various workloads.",

author = "Amin Jadidi and Mohammad Arjomand and Mahmut Kandemir and Chita Das",

note = "Publisher Copyright: {\textcopyright} 2017 ACM.; 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017 ; Conference date: 05-06-2017 Through 09-06-2017",

year = "2017",

month = jun,

day = "5",

doi = "10.1145/3078505.3078547",

language = "English (US)",

series = "SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems",

publisher = "Association for Computing Machinery, Inc",

pages = "27--28",

booktitle = "SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems",

}

Jadidi, A, Arjomand, M, Kandemir, M & Das, C 2017, A study on performance and power efficiency of dense non-volatile caches in multi-core systems. in SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Association for Computing Machinery, Inc, pp. 27-28, 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017, Urbana-Champaign, United States, 6/5/17. https://doi.org/10.1145/3078505.3078547

A study on performance and power efficiency of dense non-volatile caches in multi-core systems. / Jadidi, Amin; Arjomand, Mohammad; Kandemir, Mahmut et al.
SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. Association for Computing Machinery, Inc, 2017. p. 27-28 (SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A study on performance and power efficiency of dense non-volatile caches in multi-core systems

AU - Jadidi, Amin

AU - Arjomand, Mohammad

AU - Kandemir, Mahmut

AU - Das, Chita

PY - 2017/6/5

Y1 - 2017/6/5

N2 - This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM). Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other half are write-friendly -This asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC) mode. Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache (L3) access energy for various workloads.

AB - This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM). Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other half are write-friendly -This asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC) mode. Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache (L3) access energy for various workloads.

UR - https://www.scopus.com/pages/publications/85021785241

UR - https://www.scopus.com/pages/publications/85021785241#tab=citedBy

U2 - 10.1145/3078505.3078547

DO - 10.1145/3078505.3078547

M3 - Conference contribution

AN - SCOPUS:85021785241

T3 - SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

SP - 27

EP - 28

BT - SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

PB - Association for Computing Machinery, Inc

T2 - 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017

Y2 - 5 June 2017 through 9 June 2017

ER -

Jadidi A, Arjomand M, Kandemir M , Das C. A study on performance and power efficiency of dense non-volatile caches in multi-core systems. In SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. Association for Computing Machinery, Inc. 2017. p. 27-28. (SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems). doi: 10.1145/3078505.3078547

A study on performance and power efficiency of dense non-volatile caches in multi-core systems

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