@inproceedings{14d1e696aaa04638afce72fc32b7f52f,
title = "A switch cache design for MIN-based shared-memory multiprocessors",
abstract = "In this work, we investigate the idea of incorporating caches into selected switching elements of a multistage interconnection network (MIN)-based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hierarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence control bus, through which a write-invalidate cache coherence protocol maintains coherence of private and switch caches. The impact of the protocol on system performance is evaluated through a simulation-based performance study, which shows that it is feasible to build large shared-memory cache-coherent multiprocessor systems.",
author = "Yousif, {Mazin S.} and Das, {Chita R.}",
year = "1994",
month = jan,
day = "1",
doi = "10.1007/3-540-58430-7_38",
language = "English (US)",
isbn = "9783540584308",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "426--437",
editor = "Bruno Buchberger and Jens Volkert",
booktitle = "Parallel Processing",
address = "Germany",
note = "3rd Joint International Conference on Vector and Parallel Processing, CONPAR 1994 - VAPP VI ; Conference date: 06-09-1994 Through 08-09-1994",
}