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A switch cache design for MIN-based shared-memory multiprocessors
Mazin S. Yousif
,
Chita R. Das
Computer Science and Engineering
Research output
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Chapter in Book/Report/Conference proceeding
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Dive into the research topics of 'A switch cache design for MIN-based shared-memory multiprocessors'. Together they form a unique fingerprint.
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Keyphrases
Caching
100%
Multistage Interconnection Networks
100%
Network Applications
100%
Cache Design
100%
Shared-memory multiprocessors
100%
System Performance
25%
Shared Memory
25%
Multiprocessor Systems
25%
Cache Hierarchy
25%
Performance Studies
25%
Simulation Performance
25%
Multiprocessor
25%
Switching Element
25%
Memory Cache
25%
Bus Control
25%
Cache Coherence Protocol
25%
Coherent Control
25%
Private Cache
25%
Cache Coherent
25%
Computer Science
multistage interconnection network
100%
Shared Memory Multiprocessor
100%
multi-processor
33%
Multiprocessor System
33%
Cache Hierarchy
33%
Systems Performance
33%
Cache Coherence
33%
Shared Memory
33%
Switching Circuit
33%