A testbed for evaluation of fault-tolerant routing in multiprocessor interconnection networks

Aniruddha S. Vaidya, Chita R. Das, Anand Sivasubramaniam

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance trade-offs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults.

Original languageEnglish (US)
Pages (from-to)1052-1066
Number of pages15
JournalIEEE Transactions on Parallel and Distributed Systems
Issue number10
StatePublished - Oct 1999

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics


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