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A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches
M. S. Algudady
,
C. R. Das
, M. J. Thazhuthaveetil
Computer Science and Engineering
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
3
Scopus citations
Overview
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Dive into the research topics of 'A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches'. Together they form a unique fingerprint.
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Computer Science
Analysis Technique
50%
Cache Coherence
100%
Cache Controller
50%
Communication Delay
50%
Input Parameter
50%
multi-processor
100%
Performance Measure
50%
queueing model
50%
State Probability
50%
Systems Performance
100%
Keyphrases
Block Cache
100%
Cache Controller
33%
Coherent Control
33%
Mean Value Analysis
33%
Private Blocks
33%
Private Cache
33%
Protocol State
33%
Timing Problems
33%
Transit Delay
33%