Achieved IPC performance

Jochen Liedtke; Kevin Elphinstone; Sebastian Schonberg; Hermann Hartig; Gernot Heiser; Nayeem Islam; Trent Ray Jaeger

Achieved IPC performance

Jochen Liedtke
, Kevin Elphinstone
, Sebastian Schonberg
, Hermann Hartig
, Gernot Heiser
, Nayeem Islam
, Trent Ray Jaeger

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Extensibility can be based on cross-address-space communication or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 μ-kernel on Intel Pentium, Mips R4600 and DEC Alpha. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.

Original language	English (US)
Title of host publication	Proceedings of the Workshop on Hot Topics in Operating Systems - HOTOS
Publisher	IEEE
Pages	28-31
Number of pages	4
State	Published - 1997
Event	Proceedings of the 1997 6th Workshop on Hot Topics in Operating Systems, HOTOS - Cape Cod, MA, USA Duration: May 5 1997 → May 6 1997

Other

Other	Proceedings of the 1997 6th Workshop on Hot Topics in Operating Systems, HOTOS
City	Cape Cod, MA, USA
Period	5/5/97 → 5/6/97

All Science Journal Classification (ASJC) codes

General Computer Science

Cite this

@inproceedings{ddff5d7274104254a0c1fd7dbb8cf19f,

title = "Achieved IPC performance",

abstract = "Extensibility can be based on cross-address-space communication or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 μ-kernel on Intel Pentium, Mips R4600 and DEC Alpha. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3\% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.",

author = "Jochen Liedtke and Kevin Elphinstone and Sebastian Schonberg and Hermann Hartig and Gernot Heiser and Nayeem Islam and Jaeger, \{Trent Ray\}",

year = "1997",

language = "English (US)",

pages = "28--31",

booktitle = "Proceedings of the Workshop on Hot Topics in Operating Systems - HOTOS",

publisher = "IEEE",

note = "Proceedings of the 1997 6th Workshop on Hot Topics in Operating Systems, HOTOS ; Conference date: 05-05-1997 Through 06-05-1997",

}

TY - GEN

T1 - Achieved IPC performance

AU - Liedtke, Jochen

AU - Elphinstone, Kevin

AU - Schonberg, Sebastian

AU - Hartig, Hermann

AU - Heiser, Gernot

AU - Islam, Nayeem

AU - Jaeger, Trent Ray

PY - 1997

Y1 - 1997

N2 - Extensibility can be based on cross-address-space communication or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 μ-kernel on Intel Pentium, Mips R4600 and DEC Alpha. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.

AB - Extensibility can be based on cross-address-space communication or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 μ-kernel on Intel Pentium, Mips R4600 and DEC Alpha. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.

UR - https://www.scopus.com/pages/publications/0030651295

UR - https://www.scopus.com/pages/publications/0030651295#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0030651295

SP - 28

EP - 31

BT - Proceedings of the Workshop on Hot Topics in Operating Systems - HOTOS

PB - IEEE

T2 - Proceedings of the 1997 6th Workshop on Hot Topics in Operating Systems, HOTOS

Y2 - 5 May 1997 through 6 May 1997

ER -

Achieved IPC performance

Abstract

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All Science Journal Classification (ASJC) codes

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