TY - GEN
T1 - Achieving Crash Consistency by Employing Persistent L1 Cache
AU - Ramanathan, Akshay Krishna
AU - Shahri, Sara Mahdizadeh
AU - Xiao, Yi
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2022 EDAA.
PY - 2022
Y1 - 2022
N2 - Emerging non-volatile memory technologies promise the opportunity for maintaining persistent data in memory. How-ever, providing crash-consistency in such systems can be costly as any update to the persistent data has to reach the persistent domain in a specific order, imposing high overhead. Prior works, proposed solutions both in software (SW) and hardware (HW) to address this problem but fall short to remove this overhead completely. In this work, we propose Non-Volatile Cache (NVC) architecture design that employs a hybrid volatile, non-volatile memory cell employing monolithic 3D and Ferroelectric technol-ogy in Ll data cache to guarantee crash consistency with almost no performance overhead. We show that NVC achieves up to 5.1x speedup over state-of-the-art (SOTA) SW undo logging and 11% improvement over SOTA HW solution without yielding the conventional architecture, while incurring 7% hardware overhead.
AB - Emerging non-volatile memory technologies promise the opportunity for maintaining persistent data in memory. How-ever, providing crash-consistency in such systems can be costly as any update to the persistent data has to reach the persistent domain in a specific order, imposing high overhead. Prior works, proposed solutions both in software (SW) and hardware (HW) to address this problem but fall short to remove this overhead completely. In this work, we propose Non-Volatile Cache (NVC) architecture design that employs a hybrid volatile, non-volatile memory cell employing monolithic 3D and Ferroelectric technol-ogy in Ll data cache to guarantee crash consistency with almost no performance overhead. We show that NVC achieves up to 5.1x speedup over state-of-the-art (SOTA) SW undo logging and 11% improvement over SOTA HW solution without yielding the conventional architecture, while incurring 7% hardware overhead.
UR - http://www.scopus.com/inward/record.url?scp=85130840768&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85130840768&partnerID=8YFLogxK
U2 - 10.23919/DATE54114.2022.9774777
DO - 10.23919/DATE54114.2022.9774777
M3 - Conference contribution
AN - SCOPUS:85130840768
T3 - Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
SP - 1407
EP - 1412
BT - Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
A2 - Bolchini, Cristiana
A2 - Verbauwhede, Ingrid
A2 - Vatajelu, Ioana
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Y2 - 14 March 2022 through 23 March 2022
ER -