ACIC: Admission-Controlled Instruction Cache

Yunjin Wang, Chia Hao Chang, Anand Sivasubramaniam, Niranjan Soundararajan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The front end bottleneck in datacenter workloads has come under increased scrutiny, with the growing code footprint, involvement of numerous libraries and OS services, and the unpredictability in the instruction stream. Our examination of these workloads points to burstiness in accesses to instruction blocks, which has also been observed in data accesses [61]. Such burstiness is largely due to spatial and short-duration temporal localities, that LRU fails to recognize and optimize for, when a single cache caters to both forms of locality. Instead, we incorporate a small i-Filter as in previous works [29], [49] to separate spatial from temporal accesses. However, a simple separation does not suffice, and we additionally need to predict whether the block will continue to have temporal locality, after the burst of spatial locality. This combination of i-Filter and temporal locality predictor constitutes our Admission-Controlled Instruction Cache (ACIC). ACIC outperforms a number of state-of-the-art pollution reduction techniques (replacement algorithms, bypassing mechanisms, victim caches), providing 1.0223 speedup on the average over a baseline LRU based conventional i-cache (bridging over half of the gap between LRU and OPT) across several datacenter workloads.

Original languageEnglish (US)
Title of host publication2023 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Proceedings
PublisherIEEE Computer Society
Number of pages14
ISBN (Electronic)9781665476522
StatePublished - 2023
Event29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Montreal, Canada
Duration: Feb 25 2023Mar 1 2023

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897


Conference29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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