Aggressive dynamic execution of multimedia kernel traces

Benjamin Bishop, Robert Owens, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

There has been relatively little analytical work on processor optimizations for multimedia applications. With the introduction of MMX by Intel, it is clear that this is an area of increasing importance. Building on previous work, we propose optimizations for multimedia architectures that support independent parallel execution of instructions within dynamically assembled traces, resulting in dramatic performance improvements. Specifically, we propose simplified instruction scheduling and register renaming algorithms due to constraints on trace formation. In addition, we suggest specific instruction pool and trace cache parameters. We constructed a simulator in order to measure the benefits of these processor optimizations for multimedia applications. The simulated machine, which could fetch/decode 2 instructions per cycle, performed better than a superscalar machine that could fetch/decode 8 instructions per cycle. Execution rates as high as 7.3 instructions per cycle were achieved for the benchmarks simulated, assuming 16 instructions per trace.

Original languageEnglish (US)
Title of host publicationProceedings of the International Parallel Processing Symposium, IPPS
PublisherIEEE Comp Soc
Pages640-646
Number of pages7
ISBN (Print)0818684046
DOIs
StatePublished - 1998
EventProceedings of the 1998 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing - Orlando, FL, USA
Duration: Mar 30 1998Apr 3 1998

Other

OtherProceedings of the 1998 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing
CityOrlando, FL, USA
Period3/30/984/3/98

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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