Abstract
Increasing leakage energy consumption is an important problem for SOC-based platforms as such platforms rely on large on-chip SRAMs. While most of the previous techniques focus on hardware based leakage optimization, in this paper, we present an application access pattern oriented strategy for reducing instruction cache leakage energy. This strategy keeps track of the dynamic transitions between the procedures of a given application, and tries to keep the cache lines not used by the current procedure in a power-down state as much as possible. Our simulation results indicate significant savings in leakage energy.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International SOC Conference, SOCC 2003 |
| Editors | Dong S. Ha, Richard Auletta, John Chickanosky |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 175-178 |
| Number of pages | 4 |
| ISBN (Electronic) | 0780381823, 9780780381827 |
| DOIs | |
| State | Published - Jan 1 2003 |
| Event | IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: Sep 17 2003 → Sep 20 2003 |
Publication series
| Name | Proceedings - IEEE International SOC Conference, SOCC 2003 |
|---|
Other
| Other | IEEE International SOC Conference, SOCC 2003 |
|---|---|
| Country/Territory | United States |
| City | Portland |
| Period | 9/17/03 → 9/20/03 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
-
SDG 7 Affordable and Clean Energy
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Fingerprint
Dive into the research topics of 'An access pattern based energy management strategy for instruction caches'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver