An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks

A. Neugroschel; G. Bersuker; R. Choi; C. Cochrane; P. Lenahan; D. Heh; C. Young; C. Y. Kang; B. H. Lee; R. Jammy

doi:10.1109/IEDM.2006.346772

An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO₂ gate stacks

A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Scopus citations

Abstract

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔV_TH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO₂ interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO₂ dielectric.

Original language	English (US)
Title of host publication	2006 International Electron Devices Meeting Technical Digest, IEDM
DOIs	https://doi.org/10.1109/IEDM.2006.346772
State	Published - Dec 1 2006
Event	2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States Duration: Dec 10 2006 → Dec 13 2006

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2006 International Electron Devices Meeting, IEDM
Country/Territory	United States
City	San Francisco, CA
Period	12/10/06 → 12/13/06

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2006.346772

Cite this

Neugroschel, A., Bersuker, G., Choi, R., Cochrane, C., Lenahan, P., Heh, D., Young, C., Kang, C. Y., Lee, B. H., & Jammy, R. (2006). An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO₂ gate stacks. In 2006 International Electron Devices Meeting Technical Digest, IEDM Article 4154191 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2006.346772

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title = "An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks",

abstract = "Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.",

author = "A. Neugroschel and G. Bersuker and R. Choi and C. Cochrane and P. Lenahan and D. Heh and C. Young and Kang, {C. Y.} and Lee, {B. H.} and R. Jammy",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/IEDM.2006.346772",

language = "English (US)",

isbn = "1424404398",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

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note = "2006 International Electron Devices Meeting, IEDM ; Conference date: 10-12-2006 Through 13-12-2006",

}

Neugroschel, A, Bersuker, G, Choi, R, Cochrane, C, Lenahan, P, Heh, D, Young, C, Kang, CY, Lee, BH & Jammy, R 2006, An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO₂ gate stacks. in 2006 International Electron Devices Meeting Technical Digest, IEDM., 4154191, Technical Digest - International Electron Devices Meeting, IEDM, 2006 International Electron Devices Meeting, IEDM, San Francisco, CA, United States, 12/10/06. https://doi.org/10.1109/IEDM.2006.346772

An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO₂ gate stacks. / Neugroschel, A.; Bersuker, G.; Choi, R. et al.
2006 International Electron Devices Meeting Technical Digest, IEDM. 2006. 4154191 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Neugroschel, A.

AU - Bersuker, G.

AU - Choi, R.

AU - Cochrane, C.

AU - Lenahan, P.

AU - Heh, D.

AU - Young, C.

AU - Kang, C. Y.

AU - Lee, B. H.

AU - Jammy, R.

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AB - Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.

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