TY - GEN
T1 - An algorithm-architecture co-design framework for gridding reconstruction using FPGAs
AU - Kestur, Srinidhi
AU - Irick, Kevin
AU - Park, Sungho
AU - Al Maashri, Ahmed
AU - Narayanan, Vijaykrishnan
AU - Chakrabarti, Chaitaili
PY - 2011
Y1 - 2011
N2 - Gridding is a method of interpolating irregularly sampled data on to a uniform grid and is a critical image reconstruction step in several applications which operate on non-Cartesian sampled data. In this paper, we present an algorithm-architecture co-design framework for accelerating gridding using FPGAs. We present a parameterized hardware library for accelerating gridding to support both arbitrary and regular trajectories. We further describe our kernel automation framework which supports several kernel functions through look-up-table (LUT) based Taylor polynomial evaluation. This framework is integrated using an in-house multi-FPGA development platform which provides hardware infrastructure for integrating custom accelerators. Design-space exploration is enabled by an automation flow which allows system generation from an algorithm specification. We further provide several case studies by realizing systems for nonuniform fast Fourier transform (NuFFT) with different parameter sets and porting them on to the BEE3 platform. Results show speedups of more than 16X and 2X over existing CPU and FPGA implementations respectively, and up to 5.5 times higher performance-per-watt over a comparable GPU implementation.
AB - Gridding is a method of interpolating irregularly sampled data on to a uniform grid and is a critical image reconstruction step in several applications which operate on non-Cartesian sampled data. In this paper, we present an algorithm-architecture co-design framework for accelerating gridding using FPGAs. We present a parameterized hardware library for accelerating gridding to support both arbitrary and regular trajectories. We further describe our kernel automation framework which supports several kernel functions through look-up-table (LUT) based Taylor polynomial evaluation. This framework is integrated using an in-house multi-FPGA development platform which provides hardware infrastructure for integrating custom accelerators. Design-space exploration is enabled by an automation flow which allows system generation from an algorithm specification. We further provide several case studies by realizing systems for nonuniform fast Fourier transform (NuFFT) with different parameter sets and porting them on to the BEE3 platform. Results show speedups of more than 16X and 2X over existing CPU and FPGA implementations respectively, and up to 5.5 times higher performance-per-watt over a comparable GPU implementation.
UR - http://www.scopus.com/inward/record.url?scp=80052670557&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052670557&partnerID=8YFLogxK
U2 - 10.1145/2024724.2024860
DO - 10.1145/2024724.2024860
M3 - Conference contribution
AN - SCOPUS:80052670557
SN - 9781450306362
T3 - Proceedings - Design Automation Conference
SP - 585
EP - 590
BT - 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
PB - Institute of Electrical and Electronics Engineers Inc.
ER -