Low power optimizations have become an integral part of designing computing system. One important part of low power design is accurate and efficient power estimation during the design phase in order to meet the power specifications without a costly redesign process. Power estimation refers to the process of determining with a high level of confidence, the power consumed by a circuit/component. A lot of work has been done to come up with power estimation tools for different components of computing systems. In this work, we look at modeling one such component, The crossbar interconnect.
|Title of host publication
|Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
|John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - Jan 1 2002
|15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002 → Sep 28 2002
|Proceedings of the Annual IEEE International ASIC Conference and Exhibit
|15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
|9/25/02 → 9/28/02
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering