Abstract
In this paper, a novel architecture for transform domain motion estimation is proposed We derive a recursion equation from the algorithm and wavefront array processors are used to perform motion estimation algorithm adoptively in the transform domain according to the compression ratio. It is also shown that a higher throughput rate with the reduction of arithmetic building blocks, frame memory size and the number of memory accesses is achieved. The proposed architecture can also reconfigure to different algorithms that can be used to perform power-aware video encoding. Simulation results on video sequences of different characteristics show comparable performance of the proposed algorithm to spatial domain approaches in the aspects of PSNR and compression ratio.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1077-1082 |
| Number of pages | 6 |
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
| Volume | 17 |
| State | Published - 2004 |
| Event | Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India Duration: Jan 5 2004 → Jan 9 2004 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering