An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Keyphrases

• Silicon Nanowires (SiNWs) 100%
• Low Voltage 100%
• 6T-SRAM 100%
• SRAM Cell 100%
• Area-efficient 100%
• Gate-all-around 100%
• High Density 66%
• Three-dimensional (3D) 33%
• Design Methodology 33%
• Nanowires 33%
• MOSFET 33%
• Scale Feature 33%
• Doping Concentration 33%
• CMOS Devices 33%
• Manufacturability 33%
• System-on-chip 33%
• Semiconductor Technology 33%
• Multilevel Thresholding 33%
• Performance Projection 33%
• Circuit Performance 33%
• Reading Performance 33%
• Layout Area 33%
• Writing Performance 33%
• Heavy Doping 33%
• Silicon MOSFET 33%

Material Science

• Silicon 100%
• Nanowire 100%
• Density 66%
• Metal-Oxide-Semiconductor Field-Effect Transistor 66%
• Electronic Circuit 33%

Engineering

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Manufacturability 50%
• Nanowire Device 50%
• Circuit Performance 50%
• System-on-Chip 50%