An automatic scheduler for real-time vision applications

Mau Tsuen Yang, R. Kasturi, A. Sivasubramaniam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations


Many computes vision applications are computationally challenging especially when they need to meet real-time constraints. A major problem with special purpose systems is that they require the developers of image-processing applications to be aware of the low-level hardware design, making the task cumbersome. To avoid inflexible and expensive hardware designs, another possible alternative is a network of workstations (NOW) platform put together with off-the-shelf workstations and networking hardware. Still, one had to manually schedule an algorithm to the available processors of the NOW to make efficient use of the resources. However, this approach is time consuming and impractical for a vision system that must perform a variety of different algorithms, with new algorithms being constantly developed. Improved support for program development is absolutely necessary before the full benefits of parallel architectures can be realized for vision applications. Towards this goal, an automatic compile-time scheduler has been developed to schedule input tasks of vision applications with precedence constraints onto available processors. The scheduler exploits both spatial (parallelism) and temporal (pipelining) concurrency to make the best use of machine resources. Two important scheduling problems are addressed. First, given a task graph and a desired throughput, a schedule is constructed to achieve the desired throughput with the minimum number of processors. Second, given a task graph and a finite set of available resources, a schedule is constructed such that the throughput is maximized while meeting the resource constraints. Results from simulations show that the scheduler and proposed optimization techniques effectively tackle these problems by maximizing the processor utilization. A code generator has been developed to generate parallel programs automatically. The execution profiles of the resulting parallel programs demonstrate the feasibility of the scheduler. The tools developed in this paper make it much easier for a programmer to develop vision applications on these high-performance platforms.

Original languageEnglish (US)
Title of host publicationProceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)0769509908, 9780769509907
StatePublished - 2001
Event15th International Parallel and Distributed Processing Symposium, IPDPS 2001 - San Francisco, United States
Duration: Apr 23 2001Apr 27 2001

Publication series

NameProceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001


Other15th International Parallel and Distributed Processing Symposium, IPDPS 2001
Country/TerritoryUnited States
CitySan Francisco

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications


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