An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Vinay Saripalli; Asit Mishra; Suman Datta; Vijaykrishnan Narayanan

doi:10.1145/2024724.2024889

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Vinay Saripalli, Asit Mishra, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

65 Scopus citations

Abstract

The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications).

Original language	English (US)
Title of host publication	2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	729-734
Number of pages	6
ISBN (Print)	9781450306362
DOIs	https://doi.org/10.1145/2024724.2024889
State	Published - 2011

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Computer Science Applications
Modeling and Simulation
Electrical and Electronic Engineering

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10.1145/2024724.2024889

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Saripalli, V., Mishra, A., Datta, S., & Narayanan, V. (2011). An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 729-734). Article 5981994 (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2024724.2024889

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abstract = "The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications).",

author = "Vinay Saripalli and Asit Mishra and Suman Datta and Vijaykrishnan Narayanan",

year = "2011",

doi = "10.1145/2024724.2024889",

language = "English (US)",

isbn = "9781450306362",

series = "Proceedings - Design Automation Conference",

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An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. / Saripalli, Vinay; Mishra, Asit; Datta, Suman et al.
2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 729-734 5981994 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications).

AB - The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications).

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An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

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