An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors

Computer Science

• Coprocessor 100%
• Core Processor 100%
• Hotspot 50%
• Energy Consumption 50%
• Execution Time 50%
• Memory Operation 50%
• L1 Cache 50%
• Memory Bandwidth 50%
• High Level Synthesis 50%

Keyphrases

• Coprocessor 100%
• Irregular Codes 100%
• FPGA-based 100%
• Irregular Computation 33%
• Energy Reduction 22%
• Multiplexing 11%
• Low Power 11%
• Significant Energy 11%
• System Scaling 11%
• Execution Time 11%
• Energy Consumption Reduction 11%
• L1 Cache 11%
• Synthetic Approaches 11%
• Parallelizing 11%
• Memory Operations 11%
• Irregular Applications 11%
• Power Delay Product 11%