TY - GEN
T1 - An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs
AU - Swaminathan, Karthik
AU - Liu, Huichu
AU - Sampson, Jack
AU - Narayanan, Vijaykrishnan
PY - 2014
Y1 - 2014
N2 - For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C.
AB - For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C.
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U2 - 10.1109/ISCA.2014.6853197
DO - 10.1109/ISCA.2014.6853197
M3 - Conference contribution
AN - SCOPUS:84905440223
SN - 9781479943968
T3 - Proceedings - International Symposium on Computer Architecture
SP - 241
EP - 252
BT - 41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
Y2 - 14 June 2014 through 18 June 2014
ER -