An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Keyphrases

• System Level 100%
• Architectural Level 100%
• Steep Slope Devices 100%
• Mapping Method 50%
• Embedded Systems 50%
• Server Load 50%
• Thermal Yield 50%
• Technology Scaling 50%
• Scheduling Algorithm 50%
• 3D Circuits 50%
• 3D Architecture 50%
• Heterogeneous Technologies 50%
• Circuit Integration 50%
• Large Design Space 50%
• Thermal-aware Scheduling 50%
• Heterogeneity-aware 50%
• Process Technology 50%
• Processor Performance 50%
• Number of Points 50%
• Optimal Throughput 50%

Computer Science

• Point Throughput 100%
• Scheduling Algorithm 100%
• In-Process 100%