TY - GEN
T1 - An FPGA implementation of information theoretic visual-saliency system and its optimization
AU - Bae, Sungmin
AU - Cho, Yong Cheol Peter
AU - Park, Sungho
AU - Irick, Kevin M.
AU - Jin, Yongseok
AU - Narayanan, Vijaykrishnan
PY - 2011
Y1 - 2011
N2 - Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better than other existing models. We present an FPGA based implementation of this computationally intensive AIM algorithm to support embedded vision applications. Our implementation provides performance of processing about 4M pixels/sec for 25 basis functions with a convolution kernel size of 21 by 21 for each of the R, G, and B color-channels, when implemented on a Virtex-6 LX240T. We also provide an optimization aimed at controlling the trade-off between power consumption and latency, and performance comparisons with a GPU implementation.
AB - Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better than other existing models. We present an FPGA based implementation of this computationally intensive AIM algorithm to support embedded vision applications. Our implementation provides performance of processing about 4M pixels/sec for 25 basis functions with a convolution kernel size of 21 by 21 for each of the R, G, and B color-channels, when implemented on a Virtex-6 LX240T. We also provide an optimization aimed at controlling the trade-off between power consumption and latency, and performance comparisons with a GPU implementation.
UR - http://www.scopus.com/inward/record.url?scp=79958701449&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79958701449&partnerID=8YFLogxK
U2 - 10.1109/FCCM.2011.41
DO - 10.1109/FCCM.2011.41
M3 - Conference contribution
AN - SCOPUS:79958701449
SN - 9780769543017
T3 - Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
SP - 41
EP - 48
BT - Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
T2 - 19th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
Y2 - 1 May 2011 through 3 May 2011
ER -