An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

G. Chen; Mahmut Kandemir; I. Kolcu

doi:10.1109/SOC.2003.1241507

An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2003
Editors	Dong S. Ha, Richard Auletta, John Chickanosky
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	253-254
Number of pages	2
ISBN (Electronic)	0780381823, 9780780381827
DOIs	https://doi.org/10.1109/SOC.2003.1241507
State	Published - 2003
Event	IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: Sep 17 2003 → Sep 20 2003

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2003

Other

Other	IEEE International SOC Conference, SOCC 2003
Country/Territory	United States
City	Portland
Period	9/17/03 → 9/20/03

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/SOC.2003.1241507

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Chen, G., Kandemir, M., & Kolcu, I. (2003). An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 253-254). Article 1241507 (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241507

Chen, G. ; Kandemir, Mahmut ; Kolcu, I. / An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. Proceedings - IEEE International SOC Conference, SOCC 2003. editor / Dong S. Ha ; Richard Auletta ; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 253-254 (Proceedings - IEEE International SOC Conference, SOCC 2003).

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title = "An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures",

abstract = "In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.",

author = "G. Chen and Mahmut Kandemir and I. Kolcu",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; IEEE International SOC Conference, SOCC 2003 ; Conference date: 17-09-2003 Through 20-09-2003",

year = "2003",

doi = "10.1109/SOC.2003.1241507",

language = "English (US)",

series = "Proceedings - IEEE International SOC Conference, SOCC 2003",

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editor = "Ha, {Dong S.} and Richard Auletta and John Chickanosky",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2003",

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}

Chen, G, Kandemir, M & Kolcu, I 2003, An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. in DS Ha, R Auletta & J Chickanosky (eds), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241507, Proceedings - IEEE International SOC Conference, SOCC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 253-254, IEEE International SOC Conference, SOCC 2003, Portland, United States, 9/17/03. https://doi.org/10.1109/SOC.2003.1241507

An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. / Chen, G.; Kandemir, Mahmut; Kolcu, I.
Proceedings - IEEE International SOC Conference, SOCC 2003. ed. / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 253-254 1241507 (Proceedings - IEEE International SOC Conference, SOCC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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AU - Kandemir, Mahmut

AU - Kolcu, I.

PY - 2003

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N2 - In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.

AB - In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.

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BT - Proceedings - IEEE International SOC Conference, SOCC 2003

A2 - Ha, Dong S.

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International SOC Conference, SOCC 2003

Y2 - 17 September 2003 through 20 September 2003

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Chen G, Kandemir M, Kolcu I. An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. In Ha DS, Auletta R, Chickanosky J, editors, Proceedings - IEEE International SOC Conference, SOCC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 253-254. 1241507. (Proceedings - IEEE International SOC Conference, SOCC 2003). doi: 10.1109/SOC.2003.1241507

An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

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