Analysis of error recovery schemes for networks on chips

Srinivasan Murali; Theocharis Theocharides; N. Vijaykrishnan; Mary Jane Irwin; Luca Benini; Giovanni De Micheli

doi:10.1109/MDT.2005.104

Analysis of error recovery schemes for networks on chips

Srinivasan Murali
, Theocharis Theocharides
, N. Vijaykrishnan
, Mary Jane Irwin
, Luca Benini
, Giovanni De Micheli

Research output: Contribution to journal › Article › peer-review

283 Scopus citations

Abstract

Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

Original language	English (US)
Pages (from-to)	434-442
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/MDT.2005.104
State	Published - Sep 2005

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDT.2005.104

Cite this

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title = "Analysis of error recovery schemes for networks on chips",

abstract = "Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.",

author = "Srinivasan Murali and Theocharis Theocharides and N. Vijaykrishnan and Irwin, \{Mary Jane\} and Luca Benini and \{De Micheli\}, Giovanni",

note = "Funding Information: This research is supported by the Marco Gigascale Systems Research Center and the US National Science Foundation under contract CCR-0305718.",

year = "2005",

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AU - Murali, Srinivasan

AU - Theocharides, Theocharis

AU - Vijaykrishnan, N.

AU - Irwin, Mary Jane

AU - Benini, Luca

AU - De Micheli, Giovanni

N1 - Funding Information: This research is supported by the Marco Gigascale Systems Research Center and the US National Science Foundation under contract CCR-0305718.

PY - 2005/9

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N2 - Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

AB - Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

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M3 - Article

AN - SCOPUS:27344448860

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EP - 442

JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

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Analysis of error recovery schemes for networks on chips

Abstract

All Science Journal Classification (ASJC) codes

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