TY - GEN
T1 - Analysis of soft error rate in flip-flops and scannable latches
AU - Ramanarayanan, R.
AU - Degalahal, V.
AU - Vijaykrishnan, N.
AU - Irwin, M. J.
AU - Duarte, D.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.
AB - Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.
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U2 - 10.1109/SOC.2003.1241499
DO - 10.1109/SOC.2003.1241499
M3 - Conference contribution
AN - SCOPUS:70449462530
T3 - Proceedings - IEEE International SOC Conference, SOCC 2003
SP - 231
EP - 234
BT - Proceedings - IEEE International SOC Conference, SOCC 2003
A2 - Ha, Dong S.
A2 - Auletta, Richard
A2 - Chickanosky, John
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International SOC Conference, SOCC 2003
Y2 - 17 September 2003 through 20 September 2003
ER -