TY - GEN
T1 - Analyzing energy-delay behavior in room temperature single electron transistors
AU - Saripalli, Vinay
AU - Narayanan, Vijaykrishnan
AU - Datta, Suman
PY - 2010
Y1 - 2010
N2 - This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.
AB - This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.
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U2 - 10.1109/VLSI.Design.2010.48
DO - 10.1109/VLSI.Design.2010.48
M3 - Conference contribution
AN - SCOPUS:77949942368
SN - 9780769539287
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 399
EP - 404
BT - VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems
T2 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010
Y2 - 3 January 2010 through 7 January 2010
ER -