Analyzing energy-delay behavior in room temperature single electron transistors

Vinay Saripalli; Vijaykrishnan Narayanan; Suman Datta

doi:10.1109/VLSI.Design.2010.48

Analyzing energy-delay behavior in room temperature single electron transistors

Vinay Saripalli
, Vijaykrishnan Narayanan
, Suman Datta

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.

Original language	English (US)
Title of host publication	VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems
Pages	399-404
Number of pages	6
DOIs	https://doi.org/10.1109/VLSI.Design.2010.48
State	Published - 2010
Event	23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010 - Bangalore, India Duration: Jan 3 2010 → Jan 7 2010

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Other

Other	23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010
Country/Territory	India
City	Bangalore
Period	1/3/10 → 1/7/10

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI.Design.2010.48

Cite this

Saripalli, V., Narayanan, V., & Datta, S. (2010). Analyzing energy-delay behavior in room temperature single electron transistors. In VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems (pp. 399-404). Article 5401213 (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSI.Design.2010.48

@inproceedings{a5613234f6d94530abc6e9352764d7d7,

title = "Analyzing energy-delay behavior in room temperature single electron transistors",

abstract = "This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.",

author = "Vinay Saripalli and Vijaykrishnan Narayanan and Suman Datta",

year = "2010",

doi = "10.1109/VLSI.Design.2010.48",

language = "English (US)",

isbn = "9780769539287",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "399--404",

booktitle = "VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems",

note = "23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010 ; Conference date: 03-01-2010 Through 07-01-2010",

}

Saripalli, V, Narayanan, V & Datta, S 2010, Analyzing energy-delay behavior in room temperature single electron transistors. in VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems., 5401213, Proceedings of the IEEE International Conference on VLSI Design, pp. 399-404, 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010, Bangalore, India, 1/3/10. https://doi.org/10.1109/VLSI.Design.2010.48

Analyzing energy-delay behavior in room temperature single electron transistors. / Saripalli, Vinay; Narayanan, Vijaykrishnan; Datta, Suman.
VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems. 2010. p. 399-404 5401213 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Saripalli, Vinay

AU - Narayanan, Vijaykrishnan

AU - Datta, Suman

PY - 2010

Y1 - 2010

N2 - This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.

AB - This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.

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UR - https://www.scopus.com/pages/publications/77949942368#tab=citedBy

U2 - 10.1109/VLSI.Design.2010.48

DO - 10.1109/VLSI.Design.2010.48

M3 - Conference contribution

AN - SCOPUS:77949942368

SN - 9780769539287

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 399

EP - 404

BT - VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems

T2 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010

Y2 - 3 January 2010 through 7 January 2010

ER -

Saripalli V, Narayanan V, Datta S. Analyzing energy-delay behavior in room temperature single electron transistors. In VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems. 2010. p. 399-404. 5401213. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSI.Design.2010.48

Analyzing energy-delay behavior in room temperature single electron transistors

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