@inproceedings{114e3d404a244c0d8a9ede2779fd1244,
title = "Analyzing soft errors in leakage optimized SRAM design",
abstract = "Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltages cause increased leakage, smaller supply voltages and node capacitances can be a problem for soft errors. This work compares the soft error rates of some recently proposed SRAM leakage optimization approaches. Our results using designs in 70nm technology show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. Further, we demonstrate that there is a tradeoff between optimizing the leakage power and improving the immunity to soft error.",
author = "V. Degalahal and N. Vijaykrishnan and Irwin, {M. J.}",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design ; Conference date: 04-01-2003 Through 08-01-2003",
year = "2003",
doi = "10.1109/ICVD.2003.1183141",
language = "English (US)",
series = "Proceedings of the IEEE International Conference on VLSI Design",
publisher = "IEEE Computer Society",
pages = "227--233",
booktitle = "Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design",
address = "United States",
}