TY - GEN
T1 - Architecting microprocessor components in 3D design space
AU - Vaidyanathan, Balaji
AU - Hung, Wei Lun
AU - Wang, Feng
AU - Xie, Yuan
AU - Narayanan, Vijaykrishnan
AU - Irwin, Mary Jane
PY - 2007
Y1 - 2007
N2 - Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we implement a few components of a microprocessor using custom design to show the potential performance and power benefits achievable through 3D integration under thermal constraints. We also introduce a standard cell based 3D design flow which leverages the commercial 2D design tools. Using this design flow we provide performance results of wide range of arithmetic units in 3D, thus introducing a fast method to analyze the performance benefits of 3D designs. In contrast to prior work, which mostly investigates single components of a processor, our work takes multiple components into consideration and the experimental results are promising in terms of delay and power reductions. Complex designs in 3D that have equivalent performance compared to a simple 2D designs is taken for IPC improvement analysis. An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology.
AB - Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we implement a few components of a microprocessor using custom design to show the potential performance and power benefits achievable through 3D integration under thermal constraints. We also introduce a standard cell based 3D design flow which leverages the commercial 2D design tools. Using this design flow we provide performance results of wide range of arithmetic units in 3D, thus introducing a fast method to analyze the performance benefits of 3D designs. In contrast to prior work, which mostly investigates single components of a processor, our work takes multiple components into consideration and the experimental results are promising in terms of delay and power reductions. Complex designs in 3D that have equivalent performance compared to a simple 2D designs is taken for IPC improvement analysis. An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology.
UR - http://www.scopus.com/inward/record.url?scp=41549108607&partnerID=8YFLogxK
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U2 - 10.1109/VLSID.2007.41
DO - 10.1109/VLSID.2007.41
M3 - Conference contribution
AN - SCOPUS:41549108607
SN - 0769527620
SN - 9780769527628
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 103
EP - 108
BT - Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
T2 - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
Y2 - 6 January 2007 through 10 January 2007
ER -