Abstract
Fractal image compression has many features that makes it a powerful compression scheme, but it has been mainly restricted to archival storage due to its time consuming encoding algorithm. In this paper, we take a known quad-tree fractal encoding algorithm and design an ASIC parallel image processing array that can encode reasonably sized gray-scale images in real-time. In designing this architecture, we include novel optimizations that result in speed improvements at the algorithmic, architectural, and circuit levels.
| Original language | English (US) |
|---|---|
| Pages | 3-11 |
| Number of pages | 9 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors - Chicago, IL, USA Duration: Aug 19 1996 → Aug 21 1996 |
Other
| Other | Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors |
|---|---|
| City | Chicago, IL, USA |
| Period | 8/19/96 → 8/21/96 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications