Architectural level hierarchical power estimation of control units

Rita Yu Chen, Mary Jane Irwin, Raminder S. Bajwa

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper presents a novel technique used to estimate the power dissipation of control units at the architectural level. Based on the instruction stream and output signals of the control units, this approach provides accurate power consumption data without any knowledge of their logic structures. It is a top-down hierarchical method which can handle random logic control units as well as ROM and PLA based control units. The upper-level power estimation analyzes the instructions through their formats, and produces an efficient energy model for instruction format transitions. The lower-level estimation is performed for each instruction format by tracing the transitions of output signals. For simple logic control units, predictable internal signals can be used instead of output signals. We have applied this technique into an architectural level power estimator of a real processor. The accuracy of the estimator is demonstrated by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. The results show that our estimation approach for control units can provide more accurate solution than statistical analysis and is more efficient than conventional look-up table based methods.

Original languageEnglish (US)
Pages (from-to)211-215
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - 1998

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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