Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse

Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin; Hyoukjun Kwon; Venkata Chaitanya; Krishna Chekuri; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; Saibal Mukhopadhyay; Tushar Krishna; Sung Kyu Lim

doi:10.1145/3316781.3317775

Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya, Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

34 Scopus citations

Abstract

A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paperwe present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

Original language	English (US)
Title of host publication	Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1145/3316781.3317775
State	Published - Jun 2 2019
Event	56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States Duration: Jun 2 2019 → Jun 6 2019

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	56th Annual Design Automation Conference, DAC 2019
Country/Territory	United States
City	Las Vegas
Period	6/2/19 → 6/6/19

All Science Journal Classification (ASJC) codes

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

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10.1145/3316781.3317775

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Kim, J., Murali, G., Park, H., Qin, E., Kwon, H., Chaitanya, V., Chekuri, K., Dasari, N., Singh, A., Lee, M., Torun, H. M., Roy, K., Swaminathan, M., Mukhopadhyay, S., Krishna, T., & Lim, S. K. (2019). Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019 Article a178 (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3316781.3317775

@inproceedings{3570db2012aa47099b643bfec0c4513f,

title = "Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse",

abstract = "A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paperwe present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.",

author = "Jinwoo Kim and Gauthaman Murali and Heechun Park and Eric Qin and Hyoukjun Kwon and Venkata Chaitanya and Krishna Chekuri and Nihar Dasari and Arvind Singh and Minah Lee and Torun, {Hakki Mert} and Kallol Roy and Madhavan Swaminathan and Saibal Mukhopadhyay and Tushar Krishna and Lim, {Sung Kyu}",

note = "Funding Information: This research is funded by the DARPA CHIPS project under Award N00014-17-1-2950. Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.; 56th Annual Design Automation Conference, DAC 2019 ; Conference date: 02-06-2019 Through 06-06-2019",

year = "2019",

month = jun,

day = "2",

doi = "10.1145/3316781.3317775",

language = "English (US)",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019",

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Kim, J, Murali, G, Park, H, Qin, E, Kwon, H, Chaitanya, V, Chekuri, K, Dasari, N, Singh, A, Lee, M, Torun, HM, Roy, K, Swaminathan, M, Mukhopadhyay, S, Krishna, T & Lim, SK 2019, Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse. in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019., a178, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 56th Annual Design Automation Conference, DAC 2019, Las Vegas, United States, 6/2/19. https://doi.org/10.1145/3316781.3317775

Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse. / Kim, Jinwoo; Murali, Gauthaman; Park, Heechun et al.
Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a178 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse

AU - Kim, Jinwoo

AU - Murali, Gauthaman

AU - Park, Heechun

AU - Qin, Eric

AU - Kwon, Hyoukjun

AU - Chaitanya, Venkata

AU - Chekuri, Krishna

AU - Dasari, Nihar

AU - Singh, Arvind

AU - Lee, Minah

AU - Torun, Hakki Mert

AU - Roy, Kallol

AU - Swaminathan, Madhavan

AU - Mukhopadhyay, Saibal

AU - Krishna, Tushar

AU - Lim, Sung Kyu

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N2 - A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paperwe present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

AB - A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paperwe present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

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M3 - Conference contribution

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 56th Annual Design Automation Conference, DAC 2019

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ER -

Kim J, Murali G, Park H, Qin E, Kwon H, Chaitanya V et al. Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. a178. (Proceedings - Design Automation Conference). doi: 10.1145/3316781.3317775

Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse

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