TY - JOUR
T1 - Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
AU - Bajwa, Raminder Singh
AU - Owens, Robert Michael
AU - Irwin, Mary Jane
N1 - Funding Information:
Manuscript received October 26, 1992, revised April 21, 1993. This work was supported in part by the National Science Foundation under Grants MIP- 9 102500 and CDA-89 14587. The authors are with the Department of Computer Science and Engineering at The Pennsylvania State University, University Park, PA 16802 USA IEEE Log Number 940291 8
PY - 1994/10
Y1 - 1994/10
N2 - In this paper. we study the relative performance of three different massively parallel fine-grain, VLSI, control-flow architectures. The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAM's making it suitable for systolic MIMD/MISD computation. All three architectures are organized as two-dimensional, near-neighbor mesh connected, array of processors. All three are very similar in their construction, and in then control and data-flow requirements. The custom hardware for all three architectures was built using the same technology. We compare and contrast the performance of these three VLSI architectures for a select set of applications. To evaluate the computational power of the three architectures we use the area time product, AT, as the metric. The three designs are known to perform well in their niche applications and we find that for non-niche applications all three designs are comparable in power to within a small constant factor. The performance of the Mux-based SIMD architecture is better in general than the other two in terms of speed though the associative architecture is found to out-perform the SIMD architecture for certain numeric applications like the FFT and matrix multiplication in the AT sense.
AB - In this paper. we study the relative performance of three different massively parallel fine-grain, VLSI, control-flow architectures. The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAM's making it suitable for systolic MIMD/MISD computation. All three architectures are organized as two-dimensional, near-neighbor mesh connected, array of processors. All three are very similar in their construction, and in then control and data-flow requirements. The custom hardware for all three architectures was built using the same technology. We compare and contrast the performance of these three VLSI architectures for a select set of applications. To evaluate the computational power of the three architectures we use the area time product, AT, as the metric. The three designs are known to perform well in their niche applications and we find that for non-niche applications all three designs are comparable in power to within a small constant factor. The performance of the Mux-based SIMD architecture is better in general than the other two in terms of speed though the associative architecture is found to out-perform the SIMD architecture for certain numeric applications like the FFT and matrix multiplication in the AT sense.
UR - http://www.scopus.com/inward/record.url?scp=0028517460&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028517460&partnerID=8YFLogxK
U2 - 10.1109/12.324538
DO - 10.1109/12.324538
M3 - Article
AN - SCOPUS:0028517460
SN - 0018-9340
VL - 43
SP - 1121
EP - 1128
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 10
ER -