Arithmetic unit design using 180nm TSV-based 3D stacking technology

J. Ouyang; G. Sun; Y. Chen; L. Duan; T. Zhang; Y. Xie; M. J. Irwin

doi:10.1109/3DIC.2009.5306565

Arithmetic unit design using 180nm TSV-based 3D stacking technology

J. Ouyang, G. Sun, Y. Chen, L. Duan, T. Zhang, Y. Xie, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Scopus citations

Abstract

We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.

Original language	English (US)
Title of host publication	2009 IEEE International Conference on 3D System Integration, 3DIC 2009
DOIs	https://doi.org/10.1109/3DIC.2009.5306565
State	Published - 2009
Event	2009 IEEE International Conference on 3D System Integration, 3DIC 2009 - San Francisco, CA, United States Duration: Sep 28 2009 → Sep 30 2009

Publication series

Name	2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Other

Other	2009 IEEE International Conference on 3D System Integration, 3DIC 2009
Country/Territory	United States
City	San Francisco, CA
Period	9/28/09 → 9/30/09

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/3DIC.2009.5306565

Cite this

@inproceedings{ac200156d83647ab9654d7820467651b,

title = "Arithmetic unit design using 180nm TSV-based 3D stacking technology",

abstract = "We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.",

author = "J. Ouyang and G. Sun and Y. Chen and L. Duan and T. Zhang and Y. Xie and Irwin, {M. J.}",

year = "2009",

doi = "10.1109/3DIC.2009.5306565",

language = "English (US)",

isbn = "9781424445127",

series = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009",

booktitle = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009",

note = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009 ; Conference date: 28-09-2009 Through 30-09-2009",

}

Ouyang, J, Sun, G, Chen, Y, Duan, L, Zhang, T, Xie, Y & Irwin, MJ 2009, Arithmetic unit design using 180nm TSV-based 3D stacking technology. in 2009 IEEE International Conference on 3D System Integration, 3DIC 2009., 5306565, 2009 IEEE International Conference on 3D System Integration, 3DIC 2009, 2009 IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, CA, United States, 9/28/09. https://doi.org/10.1109/3DIC.2009.5306565

TY - GEN

T1 - Arithmetic unit design using 180nm TSV-based 3D stacking technology

AU - Ouyang, J.

AU - Sun, G.

AU - Chen, Y.

AU - Duan, L.

AU - Zhang, T.

AU - Xie, Y.

AU - Irwin, M. J.

PY - 2009

Y1 - 2009

N2 - We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.

AB - We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.

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DO - 10.1109/3DIC.2009.5306565

M3 - Conference contribution

AN - SCOPUS:70549092211

SN - 9781424445127

T3 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

BT - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

T2 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Y2 - 28 September 2009 through 30 September 2009

ER -

Arithmetic unit design using 180nm TSV-based 3D stacking technology

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