TY - GEN
T1 - Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window
AU - Jiang, Zhouhang
AU - Xiao, Yi
AU - Chatterjee, Swetaki
AU - Mulaosmanovic, Halid
AU - Duenkel, Stefan
AU - Soss, Steven
AU - Beyer, Sven
AU - Joshi, Rajiv
AU - Chauhan, Yogesh S.
AU - Amrouch, Hussam
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Funding Information:
theamplificationeffect.Usinga fixedPFE during memory read References: [1] S. Salahuddin et al., IEDM 2021; [2] H. Mulaosmanovic for different tFE, the MW linearly increases with tFEas expected et al., Nanoscale 2021; [3] H. K. Lim et al., TED 1983; [4] K. Ni et al., and the thicker the read gate oxide (tBOX), the larger the [7]T.Poirouxetal.,TED2015;[8]S.Dengetal.,VLSI2020IEDM2021; [5]X.Tianetal.,APL2018; [6]S.Dünkeletal.,IEDM2017; amplification. In practice, the remnant polarization decreases Acknowledgment: This work was supportedby U.S. Departmentof Energy, with the tFE scaling (Fig.3(e)) [5], which causes a sub-linear Centersprogramunder AwardNumber DE-SC0021118andArmyResearchOfficeofScience,OfficeofBasicEnergySciencesEnergyFrontierResearch Office under Grant Number W911NF-21-1-0341.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this work, we applied the asymmetric double-gate concept to decouple the tradeoff between ferroelectric (FE) thickness (tFE) scaling and memory window (MW) reduction in ferroelectric FET (FeFET). We demonstrate that: i) separating read and write gates and adopting a thick non-FE dielectric gate used for reading can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled tFE (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for tFE scaling.
AB - In this work, we applied the asymmetric double-gate concept to decouple the tradeoff between ferroelectric (FE) thickness (tFE) scaling and memory window (MW) reduction in ferroelectric FET (FeFET). We demonstrate that: i) separating read and write gates and adopting a thick non-FE dielectric gate used for reading can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled tFE (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for tFE scaling.
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U2 - 10.1109/VLSITechnologyandCir46769.2022.9830172
DO - 10.1109/VLSITechnologyandCir46769.2022.9830172
M3 - Conference contribution
AN - SCOPUS:85135242198
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 395
EP - 396
BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Y2 - 12 June 2022 through 17 June 2022
ER -