Asymmetrically reliable caches for multicore architectures under performance and energy constraints

Sanem Arslan, Haluk Rahmi Topcuoglu, Mahmut Taylan Kandemir, Oguz Tosun

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Cache structures in a multicore system are more vulnerable to soft errors due to high transistor density. Protecting all caches unselectively has notable overhead on performance and energy consumption. In this study, we propose asymmetrically reliable caches to supply reliability need of the system using sufficient additional hardware under the performance and energy constraints. In our framework, a chip multiprocessor is composed of a high reliability core which has ECC protection, and a set of low reliability cores which have no protection on their data caches. Between two types of cores, there is also a middle-level reliability core which has only parity check. Application threads are mapped on the different cores in terms of reliability based on their critical data usage. The experimental results for selected applications show that our proposed techniques improve reliability with considerable performance and energy overhead on the average compared to traditional unsafe caches.

Original languageEnglish (US)
Pages (from-to)1819-1833
Number of pages15
JournalCluster Computing
Issue number4
StatePublished - Dec 1 2016

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications


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