@inproceedings{75bfcbef8a734e958a1f33187d2e5cee,
title = "Automated Generation of All-Digital 1/0 Library Cells for System-In-Package Integration of Multiple Dies",
abstract = "This paper presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. We demonstrate that automated I/O library cell generation can reduce maximum die-to-die communication delay or energy for a given multi-die SiP design and associated interposer wire traces. The proposed flow is demonstrated considering 28nm CMOS technology and interposer based SiP integration.",
author = "M. Lee and A. Singh and Torun, {H. M.} and J. Kim and S. Lim and M. Swaminathan and S. Mukhopadhyay",
note = "Funding Information: ACKNOWLEDGEMENT This material is based on work supported by the DARPA CHIPS project (#N00014-17-1-2950). Publisher Copyright: {\textcopyright} 2018 IEEE.; 27th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2018 ; Conference date: 14-10-2018 Through 17-10-2018",
year = "2018",
month = nov,
day = "13",
doi = "10.1109/EPEPS.2018.8534223",
language = "English (US)",
series = "EPEPS 2018 - IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "65--67",
booktitle = "EPEPS 2018 - IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems",
address = "United States",
}