TY - JOUR
T1 - Automated I/O library generation for interposer-based system-in-package integration of multiple heterogeneous dies
AU - Lee, Minah
AU - Singh, Arvind
AU - Torun, Hakki Mert
AU - Kim, Jinwoo
AU - Lim, Sung Kyu
AU - Swaminathan, Madhavan
AU - Mukhopadhyay, Saibal
N1 - Funding Information:
Manuscript received July 15, 2019; revised October 15, 2019; accepted October 21, 2019. Date of publication November 14, 2019; date of current version January 15, 2020. This work was supported by the Defense Advanced Research Projects Agency (DARPA) Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) Program under Grant No. N00014-17-1-2950. Recommended for publication by Associate Editor M. G. Telescu upon evaluation of reviewers’ comments. (Corresponding author: Minah Lee.) The authors are with the Department of Electrical and Computing Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: minah.lee@gatech.edu).
Publisher Copyright:
© 2011-2012 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign.
AB - System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign.
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U2 - 10.1109/TCPMT.2019.2953659
DO - 10.1109/TCPMT.2019.2953659
M3 - Article
AN - SCOPUS:85078254992
SN - 2156-3950
VL - 10
SP - 111
EP - 122
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 1
M1 - 8901409
ER -