Abstract
System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign.
Original language | English (US) |
---|---|
Article number | 8901409 |
Pages (from-to) | 111-122 |
Number of pages | 12 |
Journal | IEEE Transactions on Components, Packaging and Manufacturing Technology |
Volume | 10 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2020 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering