Abstract
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 120-124 |
| Number of pages | 5 |
| Journal | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
| State | Published - 2004 |
| Event | ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States Duration: Nov 7 2004 → Nov 11 2004 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
