Carrier transport in amorphous SiC/crystalline silicon heterojunctions

Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80-400 K, using current-voltage (I-V), current-temperature (I-T), capacitance-voltage (C-V), and capacitance relaxation (C-t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 10³ at ±0.5 V. At low temperatures (80-120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance-voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.