Case study of reliability-aware and low-power design

Shengqi Yang, Wenping Wang, Tiehan Lu, Wayne Wolf, N. Vijaykrishnan, Yuan Xie

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

Original languageEnglish (US)
Article number4553751
Pages (from-to)861-873
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
StatePublished - Jul 2008

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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