Case study of reliability-aware and low-power design

Shengqi Yang; Wenping Wang; Tiehan Lu; Wayne Wolf; N. Vijaykrishnan; Yuan Xie

doi:10.1109/TVLSI.2008.2000460

Case study of reliability-aware and low-power design

Shengqi Yang
, Wenping Wang
, Tiehan Lu
, Wayne Wolf
, N. Vijaykrishnan
, Yuan Xie

Computer Science and Engineering

Research output: Contribution to journal › Article › peer-review

14 Scopus citations

Abstract

Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

Original language	English (US)
Article number	4553751
Pages (from-to)	861-873
Number of pages	13
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	16
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2008.2000460
State	Published - Jul 2008

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2008.2000460

Cite this

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abstract = "Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.",

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AU - Lu, Tiehan

AU - Wolf, Wayne

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AU - Xie, Yuan

PY - 2008/7

Y1 - 2008/7

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AB - Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

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Case study of reliability-aware and low-power design

Abstract

All Science Journal Classification (ASJC) codes

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