Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference

Anup Sarma; Huaipan Jiang; Ashutosh Pattnaik; Jagadish Kotra; Mahmut Taylan Kandemir; Chita R. Das

doi:10.1145/3357526.3357536

Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference

Anup Sarma
, Huaipan Jiang
, Ashutosh Pattnaik
, Jagadish Kotra
, Mahmut Taylan Kandemir
, Chita R. Das

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

The advent of machine learning (ML) and deep learning applications has led to the development of a multitude of hardware accelerators and architectural optimization techniques for parallel architectures. This is due in part to the regularity and parallelism exhibited by the ML workloads, especially convolutional neural networks (CNNs). However, CPUs continue to be one of the dominant compute fabric in data-centers today, thereby also being widely deployed for inference tasks. As CNNs grow larger, the inherent limitations of a CPU-based system become apparent, specifically in terms of main memory data movement. In this paper, we present CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption. Our experimental evaluations on a set of four different state-of-the-art CNN workloads indicate that CASH provides, on average, ∼40% and ∼18% reductions in main memory bandwidth and energy consumption, respectively.

Original language	English (US)
Title of host publication	MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems
Publisher	Association for Computing Machinery
Pages	396-408
Number of pages	13
ISBN (Electronic)	9781450372060
DOIs	https://doi.org/10.1145/3357526.3357536
State	Published - Sep 30 2019
Event	2019 International Symposium on Memory Systems, MEMSYS 2019 - Washington, United States Duration: Sep 30 2019 → Oct 3 2019

Publication series

Name	ACM International Conference Proceeding Series

Conference

Conference	2019 International Symposium on Memory Systems, MEMSYS 2019
Country/Territory	United States
City	Washington
Period	9/30/19 → 10/3/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Software
Human-Computer Interaction
Computer Vision and Pattern Recognition
Computer Networks and Communications

Access to Document

10.1145/3357526.3357536

Cite this

Sarma, A., Jiang, H., Pattnaik, A., Kotra, J., Kandemir, M. T., & Das, C. R. (2019). Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. In MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems (pp. 396-408). (ACM International Conference Proceeding Series). Association for Computing Machinery. https://doi.org/10.1145/3357526.3357536

@inproceedings{118820c8f6c8494d9177d95eff935969,

title = "Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference",

abstract = "The advent of machine learning (ML) and deep learning applications has led to the development of a multitude of hardware accelerators and architectural optimization techniques for parallel architectures. This is due in part to the regularity and parallelism exhibited by the ML workloads, especially convolutional neural networks (CNNs). However, CPUs continue to be one of the dominant compute fabric in data-centers today, thereby also being widely deployed for inference tasks. As CNNs grow larger, the inherent limitations of a CPU-based system become apparent, specifically in terms of main memory data movement. In this paper, we present CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption. Our experimental evaluations on a set of four different state-of-the-art CNN workloads indicate that CASH provides, on average, ∼40\% and ∼18\% reductions in main memory bandwidth and energy consumption, respectively.",

author = "Anup Sarma and Huaipan Jiang and Ashutosh Pattnaik and Jagadish Kotra and Kandemir, \{Mahmut Taylan\} and Das, \{Chita R.\}",

note = "Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.; 2019 International Symposium on Memory Systems, MEMSYS 2019 ; Conference date: 30-09-2019 Through 03-10-2019",

year = "2019",

month = sep,

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doi = "10.1145/3357526.3357536",

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Sarma, A, Jiang, H, Pattnaik, A, Kotra, J, Kandemir, MT & Das, CR 2019, Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. in MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems. ACM International Conference Proceeding Series, Association for Computing Machinery, pp. 396-408, 2019 International Symposium on Memory Systems, MEMSYS 2019, Washington, United States, 9/30/19. https://doi.org/10.1145/3357526.3357536

Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. / Sarma, Anup; Jiang, Huaipan; Pattnaik, Ashutosh et al.
MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, 2019. p. 396-408 (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Cash

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AU - Sarma, Anup

AU - Jiang, Huaipan

AU - Pattnaik, Ashutosh

AU - Kotra, Jagadish

AU - Kandemir, Mahmut Taylan

AU - Das, Chita R.

PY - 2019/9/30

Y1 - 2019/9/30

N2 - The advent of machine learning (ML) and deep learning applications has led to the development of a multitude of hardware accelerators and architectural optimization techniques for parallel architectures. This is due in part to the regularity and parallelism exhibited by the ML workloads, especially convolutional neural networks (CNNs). However, CPUs continue to be one of the dominant compute fabric in data-centers today, thereby also being widely deployed for inference tasks. As CNNs grow larger, the inherent limitations of a CPU-based system become apparent, specifically in terms of main memory data movement. In this paper, we present CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption. Our experimental evaluations on a set of four different state-of-the-art CNN workloads indicate that CASH provides, on average, ∼40% and ∼18% reductions in main memory bandwidth and energy consumption, respectively.

AB - The advent of machine learning (ML) and deep learning applications has led to the development of a multitude of hardware accelerators and architectural optimization techniques for parallel architectures. This is due in part to the regularity and parallelism exhibited by the ML workloads, especially convolutional neural networks (CNNs). However, CPUs continue to be one of the dominant compute fabric in data-centers today, thereby also being widely deployed for inference tasks. As CNNs grow larger, the inherent limitations of a CPU-based system become apparent, specifically in terms of main memory data movement. In this paper, we present CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption. Our experimental evaluations on a set of four different state-of-the-art CNN workloads indicate that CASH provides, on average, ∼40% and ∼18% reductions in main memory bandwidth and energy consumption, respectively.

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Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference

Abstract

Publication series

Conference

UN SDGs

All Science Journal Classification (ASJC) codes

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