Characterization of a small peripheral array package

Jie Hao; Andre Richter; Joy Laskar; Madhavan Swaminathan; J. Mosley

doi:10.1109/96.533889

Characterization of a small peripheral array package

Jie Hao
, Andre Richter
, Joy Laskar
, Madhavan Swaminathan
, J. Mosley

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This paper provides details on a very small peripheral array (VSPA) cavity package with high I/O's that is surface mountable on a printed circuit board (PCB). The package consists of 320 leads and measures 27 mm on a side. This paper discusses the package attributes, comparison to equivalent packages, and characterization of the package parasitics up to 3.5 GHz.

Original language	English (US)
Pages (from-to)	512-517
Number of pages	6
Journal	IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging
Volume	19
Issue number	3
DOIs	https://doi.org/10.1109/96.533889
State	Published - Aug 1996

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/96.533889

Cite this

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title = "Characterization of a small peripheral array package",

abstract = "This paper provides details on a very small peripheral array (VSPA) cavity package with high I/O's that is surface mountable on a printed circuit board (PCB). The package consists of 320 leads and measures 27 mm on a side. This paper discusses the package attributes, comparison to equivalent packages, and characterization of the package parasitics up to 3.5 GHz.",

author = "Jie Hao and Andre Richter and Joy Laskar and Madhavan Swaminathan and J. Mosley",

note = "Funding Information: Manuscript received October 11, 1995; revised December 12, 1995. This work was supported by the National Science Foundation Packaging Research Center under Contract EEC-9 402 723, Archistrat Technologies, Cascade Mi- crotech, and Hewlett-Packard. This paper was presented at the 4th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Portland, OR, October 2 4 , 1995. J. Hao, A. Richter, and J. Laskar are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GE 30332 USA. M. Swaminathan is with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GE 30332 USA. J. Mosley is with Archistrat Technology, Division of the Panda Project, Boca Raton, FL 33487 USA. Publisher Item Identifier S 1070-9894(96)05005-0.",

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AU - Richter, Andre

AU - Laskar, Joy

AU - Swaminathan, Madhavan

AU - Mosley, J.

N1 - Funding Information: Manuscript received October 11, 1995; revised December 12, 1995. This work was supported by the National Science Foundation Packaging Research Center under Contract EEC-9 402 723, Archistrat Technologies, Cascade Mi- crotech, and Hewlett-Packard. This paper was presented at the 4th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Portland, OR, October 2 4 , 1995. J. Hao, A. Richter, and J. Laskar are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GE 30332 USA. M. Swaminathan is with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GE 30332 USA. J. Mosley is with Archistrat Technology, Division of the Panda Project, Boca Raton, FL 33487 USA. Publisher Item Identifier S 1070-9894(96)05005-0.

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IS - 3

ER -

Characterization of a small peripheral array package

Abstract

All Science Journal Classification (ASJC) codes

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