ChipPower: An architecture-level leakage simulator

Yuh Fang Tsai; Ananth Hegde Ankadi; N. Vijaykrishnan; Mary Jane Irwin; Theo Theocharides

ChipPower: An architecture-level leakage simulator

Yuh Fang Tsai, Ananth Hegde Ankadi, N. Vijaykrishnan, Mary Jane Irwin, Theo Theocharides

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference
Editors	J. Chickanosky, D. Ha, R. Auletta
Pages	395-398
Number of pages	4
State	Published - 2004
Event	Proceedings - IEEE International SOC Conference - Santa Clara, CA, United States Duration: Sep 12 2004 → Sep 15 2004

Publication series

Name	Proceedings - IEEE International SOC Conference

Other

Other	Proceedings - IEEE International SOC Conference
Country/Territory	United States
City	Santa Clara, CA
Period	9/12/04 → 9/15/04

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{1829c58da9ca404f87ae7cd719055757,

title = "ChipPower: An architecture-level leakage simulator",

abstract = "Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.",

author = "Tsai, {Yuh Fang} and Ankadi, {Ananth Hegde} and N. Vijaykrishnan and Irwin, {Mary Jane} and Theo Theocharides",

year = "2004",

language = "English (US)",

isbn = "0780384458",

series = "Proceedings - IEEE International SOC Conference",

pages = "395--398",

editor = "J. Chickanosky and D. Ha and R. Auletta",

booktitle = "Proceedings - IEEE International SOC Conference",

note = "Proceedings - IEEE International SOC Conference ; Conference date: 12-09-2004 Through 15-09-2004",

}

Tsai, YF, Ankadi, AH, Vijaykrishnan, N, Irwin, MJ & Theocharides, T 2004, ChipPower: An architecture-level leakage simulator. in J Chickanosky, D Ha & R Auletta (eds), Proceedings - IEEE International SOC Conference., WB3.2, Proceedings - IEEE International SOC Conference, pp. 395-398, Proceedings - IEEE International SOC Conference, Santa Clara, CA, United States, 9/12/04.

TY - GEN

T1 - ChipPower

T2 - Proceedings - IEEE International SOC Conference

AU - Tsai, Yuh Fang

AU - Ankadi, Ananth Hegde

AU - Vijaykrishnan, N.

AU - Irwin, Mary Jane

AU - Theocharides, Theo

PY - 2004

Y1 - 2004

N2 - Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

AB - Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

UR - http://www.scopus.com/inward/record.url?scp=14844296421&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=14844296421&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:14844296421

SN - 0780384458

SN - 9780780384453

T3 - Proceedings - IEEE International SOC Conference

SP - 395

EP - 398

BT - Proceedings - IEEE International SOC Conference

A2 - Chickanosky, J.

A2 - Ha, D.

A2 - Auletta, R.

Y2 - 12 September 2004 through 15 September 2004

ER -

ChipPower: An architecture-level leakage simulator

Abstract

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