TY - GEN
T1 - Circuit design methodologies for test power reduction in nano-scaled technologies
AU - Chakravarthi, Veena S.
AU - Ghosh, Swaroop
PY - 2013
Y1 - 2013
N2 - Test power has emerged as an important design concern in nano-scaled technologies. The BIST circuitry for periodic self-test consumes significant power in hand-held electronic devices to increase battery lifetime. Reduced test power of a module allows parallel testing of multiple embedded cores in an IC. Peak and average power reduction during test contribute to enhanced reliability and improved yield. In this paper, we present circuit design methodologies to reduce test power in nano-scaled technologies. In addition to this advantage of reduced supply, testing concept is mentioned for initial testing which will give dual benefit of power and test time reduction.
AB - Test power has emerged as an important design concern in nano-scaled technologies. The BIST circuitry for periodic self-test consumes significant power in hand-held electronic devices to increase battery lifetime. Reduced test power of a module allows parallel testing of multiple embedded cores in an IC. Peak and average power reduction during test contribute to enhanced reliability and improved yield. In this paper, we present circuit design methodologies to reduce test power in nano-scaled technologies. In addition to this advantage of reduced supply, testing concept is mentioned for initial testing which will give dual benefit of power and test time reduction.
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U2 - 10.1007/978-81-322-1524-0_20
DO - 10.1007/978-81-322-1524-0_20
M3 - Conference contribution
AN - SCOPUS:84881137612
SN - 9788132215233
T3 - Lecture Notes in Electrical Engineering
SP - 139
EP - 149
BT - Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013
T2 - International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013
Y2 - 17 July 2013 through 19 July 2013
ER -