TY - GEN
T1 - COAST
T2 - 20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
AU - Aziz, Ahmedullah
AU - Shukla, Nikhil
AU - Datta, Suman
AU - Gupta, Sumeet Kumar
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/21
Y1 - 2015/9/21
N2 - We present a novel technique for optimizing the read operation of spin-transfer torque (STT) MRAMs by employing a correlated material in conjunction with a magnetic tunnel junction (MTJ). The design of the proposed memory cell is based on exploiting the orders-of-magnitude difference in the resistance of the two phases of the correlated material (CM) and triggering operation-driven phase transitions in the CM by judiciously co-optimizing devices and the memory cell. During read, the CM operates in the metallic and insulating phases when the MTJ is in the low resistance and high resistance states, respectively. This leads to superior distinguishability, read efficiency and stability. During write, the CM operates in the metallic phase, which minimizes the impact of the CM resistance on the write speed. Our analysis shows that CM amplifies the cell tunneling magneto-resistance from 107% (for the standard STT MRAM) to 1878% (for the proposed cell) leading to 68% higher sense margin. In addition, 45% enhancement in the read disturb margin and 36% reduction in the cell read power is achieved. At the same time, the write asymmetry associated with different state transitions is mildly mitigated, leading to 9% reduction in the write power. This comes at a negligible cost of 4% larger write time. We also discuss the layout implications of our technique and propose the sharing of the CM amongst multiple cells. As a result of the sharing, the proposed technique incurs no area penalty.
AB - We present a novel technique for optimizing the read operation of spin-transfer torque (STT) MRAMs by employing a correlated material in conjunction with a magnetic tunnel junction (MTJ). The design of the proposed memory cell is based on exploiting the orders-of-magnitude difference in the resistance of the two phases of the correlated material (CM) and triggering operation-driven phase transitions in the CM by judiciously co-optimizing devices and the memory cell. During read, the CM operates in the metallic and insulating phases when the MTJ is in the low resistance and high resistance states, respectively. This leads to superior distinguishability, read efficiency and stability. During write, the CM operates in the metallic phase, which minimizes the impact of the CM resistance on the write speed. Our analysis shows that CM amplifies the cell tunneling magneto-resistance from 107% (for the standard STT MRAM) to 1878% (for the proposed cell) leading to 68% higher sense margin. In addition, 45% enhancement in the read disturb margin and 36% reduction in the cell read power is achieved. At the same time, the write asymmetry associated with different state transitions is mildly mitigated, leading to 9% reduction in the write power. This comes at a negligible cost of 4% larger write time. We also discuss the layout implications of our technique and propose the sharing of the CM amongst multiple cells. As a result of the sharing, the proposed technique incurs no area penalty.
UR - https://www.scopus.com/pages/publications/84958523741
UR - https://www.scopus.com/pages/publications/84958523741#tab=citedBy
U2 - 10.1109/ISLPED.2015.7273481
DO - 10.1109/ISLPED.2015.7273481
M3 - Conference contribution
AN - SCOPUS:84958523741
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 1
EP - 6
BT - Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 July 2015 through 24 July 2015
ER -