TY - GEN

T1 - Combined multiplication and sum-of-squares units

AU - Schulte, Michael J.

AU - Marquette, Louis

AU - Krithivasan, Shankar

AU - Walters, E. George

AU - Glossner, John

N1 - Publisher Copyright:
© 2003 IEEE.

PY - 2003

Y1 - 2003

N2 - Multiplication and squaring are important operations in digital signal processing and multimedia applications. We present designs for units that implement either multiplication, A×B, or sum-of-squares computations, A2+B2, based on an input control signal. Compared to conventional parallel multipliers, these units have a modest increase in area and delay, but allow either multiplication or sum-of-squares computations to be performed. Combined multiplication and sum-of-squares units for unsigned and two's complement operands are presented, along with integrated designs that can operate on either unsigned or two's complement operands. The designs can also be extended to work with a third accumulator operand to compute either Z+A×B or Z+A2+B2/. Synthesis results indicate that a combined multiplication and sum-of-squares unit for 32-bit two's complement operands can be implemented with roughly 15% more area and nearly the same worst case delay as a conventional 32-bit two's complement multiplier.

AB - Multiplication and squaring are important operations in digital signal processing and multimedia applications. We present designs for units that implement either multiplication, A×B, or sum-of-squares computations, A2+B2, based on an input control signal. Compared to conventional parallel multipliers, these units have a modest increase in area and delay, but allow either multiplication or sum-of-squares computations to be performed. Combined multiplication and sum-of-squares units for unsigned and two's complement operands are presented, along with integrated designs that can operate on either unsigned or two's complement operands. The designs can also be extended to work with a third accumulator operand to compute either Z+A×B or Z+A2+B2/. Synthesis results indicate that a combined multiplication and sum-of-squares unit for 32-bit two's complement operands can be implemented with roughly 15% more area and nearly the same worst case delay as a conventional 32-bit two's complement multiplier.

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U2 - 10.1109/ASAP.2003.1212844

DO - 10.1109/ASAP.2003.1212844

M3 - Conference contribution

AN - SCOPUS:4544366998

T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

SP - 204

EP - 214

BT - Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003

A2 - Deprettere, Ed

A2 - Bhattacharyya, Shuvra

A2 - Thiele, Lothar

A2 - Cavallaro, Joseph

A2 - Darte, Alain

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003

Y2 - 24 June 2003 through 26 June 2003

ER -