Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing

This paper proposes combining system-level modular redundancy with the arithmetic modularity of residue number system (RNS) arithmetic to achieve fault tolerance in high speed digital signal processing (DSP) systems. Double, triple, and quadruple modular redundancy, system-level concepts which are frequently used in commercial fault tolerant computers, are combined with RNS modularity for realizing important DSP computational kernels. The discussion includes the development of the serial-by-modulus (SBM) RNS architecture in which residue digits are processed sequentially in circuits that handle only one modular operation at a given time, thereby sacrificing speed for circuit simplicity. As a potential application of the SBM concept, a variable word length sum-of-products signal processing kernel is developed based on a serial-by-modulus RNS architecture. Due to the fact that the RNS is not a weighted number representation, if the instantaneous dynamic range requirement can be estimated it may be possible to perform the computation with only enough residue digits to provide the necessary dynamic range. The variable word length concept is demonstrated through computer simulation.